1. Field of the Invention
This invention relates generally to semiconductor fabrication technology and, more particularly, to a method of fabricating a transistor with a dielectric underlayer.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, the reduction in the channel length of a transistor also requires a reduction in the depth of the source/drain regions adjacent the gate conductor. As source/drain junctions get shallower, the implantation to prevent punch-through also gets shallower. In turn, the shallower punch-through implant tends to invade the space of the threshold voltage (V.sub.threshold or V.sub.th) implant. Thus, the concentration of boron would be greater at the surface of the silicon substrate in an N-channel metal oxide semiconductor FET (NMOSFET or NMOS transistor or NMOS), for example. This increased concentration of the punch-through dopant, in turn, tends to make the threshold voltage V.sub.th of the FET higher. Increases in the threshold voltage V.sub.th of a FET are undesirable for a number of reasons. For example, an increase in the threshold voltage V.sub.th tends to make an "enhanced mode" NMOS transistor harder to turn "ON" and may also result in the reduction of the drive current of the device.
Typically, the current flow through the channel of a MOSFET or MOS transistor is relatively unconfined. In particular, the presence of a leakage current to the substrate is certainly possible and virtually inevitable. Furthermore, in the case of complementary MOS (CMOS) structures having adjacent PMOS and NMOS transistors, the potential for latchup is usually present.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.